The present invention relates generally to the fabrication of integrated circuit devices and, more particularly, to the fabrication of antifuses in integrated circuits.
Antifuses are elements which are located between two conducting lines in an integrated circuit. The antifuse has a very high resistance (to form essentially an open circuit) in an unprogrammed ("off") state to keep the two conducting lines electrically separated. In a programmed ("on") state, the antifuse has a low resistance (to form essentially a closed circuit) to electrically connect the two conducting lines.
Ideally antifuses should have a low parasitic capacitance in the unprogrammed state and should occupy minimal layout area, with very short programming times, and should require programming voltages which are not so high as to require additional process complexity to accommodate the high programming voltages. In the programmed state the antifuse should, of course, have as low a resistance as possible.
One antifuse which has many of these advantages is disclosed in U.S. Pat. No. 4,442,507 and 4,796,074, issued to B. Roesner on Apr. 10, 1984 and Jun. 3, 1989 respectively. This antifuse is formed between a silicon layer, either a doped region in the semiconductor substrate of an integrated circuit or a doped polysilicon layer, and a metal conducting layer above.
The present invention substantially improves many of the processing steps or solves many of the deficiencies in the steps used in fabricating the disclosed present antifuse.